library verilog;
use verilog.vl_types.all;
entity registerFile is
    port(
        clock           : in     vl_logic;
        Rs_address      : in     vl_logic_vector(4 downto 0);
        Rt_address      : in     vl_logic_vector(4 downto 0);
        Rd_address      : in     vl_logic_vector(4 downto 0);
        Rd_data         : in     vl_logic_vector(31 downto 0);
        regWrite        : in     vl_logic;
        Rs_data         : out    vl_logic_vector(31 downto 0);
        Rt_data         : out    vl_logic_vector(31 downto 0)
    );
end registerFile;
